Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Front End Engineer responsible for implementing complex SOC using ARM architecture. As a Front End Engineer you will work on SoC RTL and its implementation and quality checks like synthesis, lint, CDC and other aspects of SoC implementation process. You will be involved in these checks and flow management for both high performance, multi million gate complex IPs and SoC. You will be responsible for doing the Power, Performance and Area analysis and optimization as well as implementation quality of the entire ASIC.
Requirements
- Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI
- 2+ years of practical experience in front end design implementation
- Strong fundamentals in digital ASIC design
- Understanding of IP and SoC design and implementation methodology and challenges
- Understanding of one or more of design flows like Synthesis, Constraint development and verification, STA, Floorplanning, Lint, CDC, Low Power and UPF, Power estimation, Formal verification, ECO implementation
- Good hands on expertise with industry standard implementation and verification tools like – Synopsys Design Compiler/Fusion Compiler, Formality/LEC, Spyglass Lint and CDC, VCLP, Power Estimator tools like Power Explorer, PrimePower, Synopsys RTL Architect, Constraint Analyzer tools, Conformal ECO
- Able to work with TCL and Perl scripting and flow automation
- Excellent communication and team work
Responsibilities
- Work on SoC and IP implementation methodology and flow for meeting PPA goals
- Contribute to automate flows to enhance usability by design team as well as improve development schedule
- Provide early feedback on design issues and solutions
- Work with Backend team in realizing PPA goals during PnR
- Work with IP and SoC Design team in optimizing the design to meet PPA goals
- Run and ensure all the quality checks on IP and SoC RTL for first pass success of ASIC
Job Location: Bangalore