Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Verification Engineer taking on IP and SoC level verification challenges. As a Verification you will have a focus on verification of Multi-core, complex, high performance ASIC. Your work will be to understand the internal requirements and complexities of our SOC and design the verification environment and solutions. You will help design the SoC and IP verification methodology, environment, test plan and tests as per your capabilities. You will also work with design team to make sure that high quality verification is achieved for first pass success of the SoC.

Requirements

• BE/BS degree (Masters preferred) in Electrical/Electronics/VLSI Engineering with 2+ years of relevant verification experience
• Strong fundamentals in digital ASIC design and verification
• Expertise in ARM cores and related infrastructure (like Coresight, NIC/NOC, other bus interconnects etc.)
• Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC
• Strong experience with Verilog, SystemVerilog, UVM and/or other
• Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART is desirable
• Understanding of IP designs and verification requirements
• Strong test creation, debug capability and functional coverage understanding
• Understanding of Gate Level Simulations (GLS) with timing and related debug capability
• Excellent communication and leadership quality to technically mentor and lead a team of verification engineers

Responsibilities

• Develop verification environment and test plans driven by functional coverage
• Develop test cases and execute them for verification of the design (both IP and SoC level)
• Run verification simulations and debug design and RTL issues
• Work closely with design team for continuous improvement of design quality through verification
• Review the test plans, verification tests and coverage for other team members
• Contribute on GLS, emulation, FPGA based and Post Si validation